1. Field of the Invention
The present invention relates to a semiconductor device in which a transistor is formed on the (551) plane of silicon.
2. Description of the Related Art
In the current integrated circuit formed from a CMOS transistor, the resistive component of the source/drain contact of the transistor hampers an improvement in characteristic of the integrated circuit. The effective transconductance gmeff in a case that the source and drain electrodes have a series resistance RS is given as a function of the intrinsic transconductance gmi that represents the current driving capability of the transistor when it has no resistive component:
                              g          meff                =                              g            mi                                1            +                                          R                S                            ⁢                              g                mi                                                                        (        1        )            
As the series resistance RS rises, the effective transconductance gmeff can be increased only slightly even by increasing the intrinsic transconductance gmi, so the operating speed of the integrated circuit does not improve. It is of prime importance to thoroughly decrease the series resistance RS in an ultraminiaturized transistor which has a relatively high intrinsic transconductance gmi. The series resistance RS of the source and drain electrodes of the transistor includes the contact resistance RC between the n+ or p+ region and the metal electrodes in the source and drain regions. If the source and drain regions have high impurity concentrations, the contact resistance RC is given by:
                              R          C                ∝                  exp          ⁡                      [                                                            4                  ⁢                                                                                    m                        p                                            ⁢                                              ɛ                        S                                                                                                              h                  /                                      (                                          2                      ⁢                      π                                        )                                                              ⁢                              (                                                      ϕ                    b                                                                              N                      A                                                                      )                                      ]                                              (        2        )            where h is Planck's constant, mp is the effective mass of electrons or holes, ∈s is the dielectric constant of silicon, NA is the electron density or hole density in the n+ or p+ region, and φb is the barrier height between the metal electrodes (silicide) and the n+ or p+ region. To decrease the contact resistance, it is necessary to increase the carrier density NA at the contact interface and lower the barrier height φb between the metal electrodes (silicide) and the silicon.
A transistor formed on the (551) plane of silicon is advantageous to increase the intrinsic transconductance gmi. However, it is difficult to form a silicide layer with characteristics that are good for both the (551) plane of the p-type region and that in the n-type region. A silicide layer formed on the (551) plane of the p-type region becomes an uneven film instead of a uniform film unless it has a certain thickness. On the other hand, if a silicide layer formed on the (551) plane of the n-type region has the same thickness as that formed on the (551) plane of the p-type region, its barrier height is so high that the contact resistance RC or the series resistance RS increases, thus hampering an improvement in operating speed of an integrated circuit.